Various types of systems have been provided in the prior art for converting an analog voltage to digital signals (currents or voltages) representative of such analog voltage. One type of system often used in the prior art to provide such conversion has been known as a "flash converter". In a flash converter, an analog input signal representative of the analog value to be converted digitally is introduced to a first input of a differential amplifier in each of a plurality of repetitive cells. An individual one of a plurality of progressive fractions in a reference voltage is introduced to a second input of such differential amplifier. In the prior art, the differential amplifier in each
cell may have first and second branches each including a transistor such as a CMOS transistor and each having a gate, a source and a drain. The gates of the transistors in the first and second branches respectively receive the first and second inputs. The drains of the two (2) transistors in each differential amplifier have a common connection to a source of a substantially constant current.
Load bearing currents flow through the transistors in the branches in each differential amplifier in accordance with the relative values of the voltages on the gates of the transistors, the sum of these currents being the substantially constant current. Thus, a first output such as a binary "1" is produced in the differential amplifier when the input voltage exceeds the reference voltage introduced to the differential amplifier. Similarly, a second output such as a binary "0" is produced in the differential amplifier when the input voltage is less than the reference voltage introduced to the differential amplifier.
In the prior art, a plurality of comparators are provided each comparing the outputs in an individual pair of successive differential amplifiers. The analog input voltage is determined by the comparator in which opposite output voltages are produced from the differential amplifiers providing inputs to the comparator. Each comparator is programmed to provide a series of digital signals indicative of the individual one of the progressive fractions of the reference voltage introduced to one of the differential amplifiers providing inputs to the comparator.
The analog-to-digital converter discussed above is advantageous in that it can operate at high frequencies such as in the megahertz range. However, in order to determine the value of the input voltage with some accuracy and to convert this input voltage to the corresponding digital signals, a large number of amplifiers have to be provided. For example, for a converter providing a conversion of an analog signal to ten (10) binary bits, ten hundred and twenty four (1024) differential amplifiers and ten hundred and twenty three (1023) comparators would be required. When the input voltage is approximately two volts, each amplifier would have to provide a distinction between adjacent amplifiers in the order of two millivolts (2 mV.) Since this voltage is relatively small, it presents difficulties in the operation of the comparators.
The flash types of analog-to-digital converters have generally been disposed on an integrated circuit chip, particularly for a number of binary bits greater than about seven (7). Imperfections in the silicon substrate of the chip and in the methods of manufacturing the chip have produced mismatches between successive pairs of differential amplifiers. These mismatches have caused errors to be produced in the stages providing the comparison between successive pairs of differential amplifiers. These mismatches have caused errors to be produced in digital indications produced to represent the analog input signal.
Various attempts have been made to compensate for the cell mismatches produced in the converter of the prior art. For example, U.S. Pat. No. 5,175,550 issued to Kevin M. Kattman and Jeffrey G. Barrow for "Repetitive Cell Matching Technique for Integrated Circuits" and assigned of record to Analog Devices, Inc. discloses a system for, and method of providing, such compensation. In the '550 patent, a plurality of cells are provided each including a differential amplifier defined by two (2) branches. A transistor is provided in each branch. The transistor in a first one of the branches in each cell receives an input signal and the transistor in a second one of the branches in each cell receives an individual one of the progressive fractions of a reference voltage.
In the '550 patent, a plurality of load resistors are provided each connected to an individual one of the transistors in one of the first and second branches in an individual one of the cells to receive the load current flowing through such transistor. In addition, a first plurality of averaging resistors is provided each connected between the corresponding output terminals of the transistors in the first branches of successive pairs of the repetitive cells. A second plurality of averaging resistors is also provided each connected between the corresponding output terminals of the transistors in the second branches of successive pairs of the repetitive cells.
The system disclosed in the '550 patent operates to average the cell mismatches over a plurality of cells so as to reduce the inaccuracies resulting in the converted digital signals from the cell mismatches. Because of this, the system disclosed in the '550 patent reduces the differential non-linearities and integral non-linearities in the analog-to-digital converter formed from the plurality of cells. The lower the values of the averaging resistors that are provided in the first and second pluralities in the '550 patent, the greater is the improvement in the accuracy of the conversion from the analog value to the digital value. For example, in the optimum, the differential non-linearity of the system disclosed in the '550 patent is reduced by a factor of approximately three (3) (1.58 bits) in comparison to the A-D converters of the prior art.